In the field of integrated circuits, input circuits are known with "bus-hold" or "bus-keeper" features, that is, that are capable of maintaining a prescribed logic state on the bus of external lines supplied thereto even when the driver circuits driving the bus are put in a high impedance (tri-state) mode. In this way, it is possible to maintain on the lines of the bus a well defined logic state even when no circuits drive the bus, preventing leakage currents due to a not well defined logic state, or avoiding the necessity of pull-up or pull-down resistors.
A typical structure of a bus-hold input circuit includes two inverters, for example of the CMOS type, coupled to form a latch circuit which keeps and regenerates an input signal applied to a signal line coupled to the input of the input circuit. A first inverter receives the input signal and provides a regenerated output signal, which is then supplied to the remaining blocks of the integrated circuit to which the input circuit belongs. The second inverter has an input coupled to the output of the first inverter and an output coupled to the input signal line which is to be kept at a prescribed logic level, even in the absence of an external driving signal. Typically, the second inverter has a high output impedance, so to be easily driven by the driver of the external signal line, when the driver is activated. In this way, the signal line can be driven by another, stronger drive circuit.
Depending on the particular application, it is necessary that the input circuit assure, for a given voltage on the input signal line, well defined values for the so-called "sustaining current", in a bus-hold mode of operation, and for an overdrive current to be furnished to the signal line by an external driver driving the signal line. These voltage and current parameters have values that are specified, depending on the particular application, and can vary with the particular application.
Bus-hold input circuits are also known whereby the second inverter is clocked, or whereby the second inverter can be put in a high-impedance condition. In some applications it could be useful to disable the input circuit bus-hold function for a prescribed logic level on the input signal line, or even to disable the bus-hold function. This is achieved by providing, in series to P and N channel MOSFETs (pull-up and pull-down) forming the second inverter, transistors of the same type (a P-channel MOSFET in series with the pull-up, and an N-channel MOSFET in series with the pull-down) controlled by a drive signal for turning the MOSFETs ON and OFF to enable or disable the bus-hold finction, respectively, for the high or low logic states.
Additionally, bus-hold input circuits are known where the second inverter is replaced by a NAND or NOR logic gate with two inputs, one connected to the output of the first inverter and the other behaving as a control input for a control signal that, depending on its state, allows the function of the input circuit to be changed from a bus-hold function to a simple pull-up or pull-down function for the signal line coupled to the input. This is useful in applications involving microprocessors, where it is necessary to put the lines of the external bus to a prescribed logic level during the execution of particular scanning tests.
Another known bus-hold input circuit structure provides two inverters coupled in series, with the input of the first inverter coupled to the input signal line, and the output of the second inverter forming the regenerated signal which is supplied to the remaining blocks of the integrated circuit. The output of the second inverter is also coupled to the input of the first inverter and thus to the input signal line, again forming a latch circuit and maintaining the signal on the input signal line.
These input circuits are not capable of accepting input signals with voltages higher than the supply voltage of the input circuit. This feature, in the case of input circuits with a 3.3 V supply, means that the input circuits are not capable of accepting voltages of 5 V.
The reason why the proposed bus-hold input circuits are not capable of tolerating input voltages higher than their own power supply voltage is that in all the bus-hold circuits the input signal line is always connected to the drain electrode of a P-channel MOSFET of the second inverter or, more generally, of the logic gate that, together with the first inverter, forms the latch maintaining the signal on the input line. When the voltage on the input signal line exceeds the supply voltage of the input circuit by at least one turn-on threshold of a PN junction, a parasitic diode associated with the P+ drain region of the P-channel MOSFET and the N type bulk of such a MOSFET (connected to the V.sub.DD voltage of the input circuit) turns ON, setting up a direct path between V.sub.DD and the input.